This invention relates generally to semiconductor fabrication, and particularly to dielectric and barrier layers used in semiconductor fabrication. More specifically, the invention relates to methods of fabrication of hardened composite semiconductor gate oxides.
FIGS. 1A through C illustrate steps in a conventional semiconductor fabrication process on a portion of a semiconductor wafer 100. In FIG. 1A, a semiconductor substrate 101 is shown. The substrate 101 has a gate oxide layer 104 formed on its upper surface 102. The gate oxide layer 104 may be created in ways well known to those of skill in the art. For example, the gate oxide may be silicon dioxide (SiO.sub.2) generated by thermal oxidation of surface 102 of the silicon substrate 101, or may be deposited on the silicon substrate 101 by chemical vapor deposition (CVD). Typical conventional gate oxide thicknesses, for example for semiconductor devices having gate lengths from about 0.18 to 1 .mu.m, are about 25 to 200 .ANG..
As shown in FIGS. 1B and 1C, a polysilicon (poly) layer 106 is typically deposited over the following gate oxide layer 104, for example by CVD. FIG. 1B shows the wafer 100 with the poly layer 106 on the gate oxide layer 104. FIG. 1C shows the wafer 100 after the poly layer 106 has been patterned and etched to form a gate electrode 108, according to methods well known in the art. The gate electrode 108 may then be used as a mask in a self-aligned implant process to produce doped active source 110 and drain 112 regions in the substrate 101, on either side of the gate electrode 108, thereby forming an MOS transistor.
As semiconductor technology develops, semiconductor device geometries have been reduced. As a result, the various components that make up a semiconductor have been decreased in size. For example, MOS transistor gate widths have been reduced below 0.5 .mu.m to 0.35 .mu.m, 0.25 .mu.m and smaller device sizes are currently being developed. As device sizes decrease, gate dielectric layers in such devices should correspondingly become thinner. For example, in some next generation devices the channel length will be about 0.18 .mu.m and the gate oxide thickness will be about 30 .ANG.. In future generation devices both the channel length and gate oxide thickness will continue to shrink. However, thinner gate dielectrics are more susceptible to failure. Therefore, it is desirable to increase the capability of thin gate dielectrics, commonly oxides, so that they are better able to withstand the high electric fields to which they are subjected in normal operation of smaller semiconductor devices through a process referred to as "hardening".
Gate oxide hardening is required for at least three reasons. First, insufficiently hard gate oxides can break down at voltages below normal operating voltages. Second, hardened gate oxides are resistant to hot electron degradation which creates structural defects, such as dangling bonds, in gate oxides. Finally, hardened gate oxides may also be effective in preventing diffusion of dopant atoms from the gate electrode through the gate oxide into the substrate. One particularly troubling problem is boron diffusion from a polysilicon gate electrode, through the gate oxide and into the silicon substrate. Boron is mobile at typical processing temperatures. Unwanted dopant diffusion into the substrate will cause fluctuations in the semiconductor device's threshold voltage. This is particularly important in PMOS devices where boron dopant is commonly used in the polysilicon gate electrode.
Conventional methods for hardening gate oxides have involved diffusing nitrogen into a gate oxide after its formation. In this process, the gate oxide is thermally grown on a single crystal silicon substrate. Next, the gate oxide is exposed to an atmosphere containing nitrous oxide, nitric oxide, ammonia or other nitrogen source at a high temperature (about 900.degree. C.) which results in nitrogen incorporation into the gate oxide. The resulting increased concentration of nitrogen containing species in the gate oxide prevents boron diffusion into the silicon substrate, hot electron degradation and improves the breakdown resistance of the gate oxide.
Unfortunately, hardening through nitrogen incorporation through the oxidation process has some drawbacks. Among these problems are that the high temperature treatment involved in gate oxide hardening by nitrogen diffusion cuts into the fabrication process' thermal budget. In addition, hardening with an ammonia anneal introduces electron traps into the dielectric. Furthermore, because the nitrogen tends to localize at the substrate-gate oxide interface, conventional hardening does reduce boron diffusion from the gate oxide to the silicon substrate, but fails to prevent boron diffusion into the gate oxide from a doped polysilicon gate electrode. This is important since the properties of the gate oxide may be adversely affected by creation of traps in oxide by dopants such as boron.
Nitrogen implantation processes in which nitrogen ions are implanted into polysilicon gate electrodes are described in S. Haddad, et al., IEEE Electron Device Letter, 8, 58-60, 1987; T. Kuroi, et al., Tech. Dig. of the Int'l. Electron Devices Mtg. (IEDM), 325-328, 1993; S. Nakayama et al., 1996 Symposium on VLSI Technology, 228-229; A. Chou, et al., International Reliability Physics Symposium, 174-177, 1997, which are incorporated by reference herein. These processes produce a nitrogen concentration peak within the bulk polysilicon gate electrode. This effectively suppresses boron diffusion in the polysilicon and therefore cures some of the noted drawbacks in the nitrogen diffusion gate oxide hardening process. Unfortunately, the boron concentration drops off dramatically below the nitrogen concentration peak in the bulk polysilicon. The very low concentration of boron near the gate electrode-gate oxide interface results in formation of polysilicon depletion regions during device operation. Polysilicon depletion regions in the gate electrode act as non-conductive areas that effectively increase gate oxide thickness, thus degrading device performance.
Other nitridization methods have been investigated, including implantation of atomic nitrogen into the single crystal silicon substrate and growth of additional oxide on the substrate surface that incorporates the implanted nitrogen. C. T. Liu et al., High Performance 0.2 .mu.m CMOS with 25 .ANG. gate oxide grown on nitrogen implanted Si substrates, IEDM Technical Digest, 499-502 (1996). However, there are also several significant drawbacks to this approach. In particular, the crystal structure of the silicon substrate is damaged by the implant. In addition, the implant dose is limited by considerations of the effects on the channel behavior of devices with very high residual nitrogen concentrations. As a result, the creation of oxynitride bonds in the oxide layer according to this method is typically practically limited to less than one atomic percent.
It has been reported that surface regions of very thin gate oxide layers (about 4 nm) can be heavily nitridized, for example in the range of about 10 to 20 atomic percent. S. V. Hattangady et al., Ultrathin nitrogen-profile engineered gate dielectric films, IEEE International Electron Devices Meeting Technical Digest, 495-498, Dec. 8-11, 1996; D. T. Grider et al., A 0.18 .mu.m CMOS Process Using Nitrogen Profile-Engineered Gate Dielectrics, IEEE 1997 Symposium on VLSI Technology Digest of Technical Papers, 47-48, Jun. 10-12, 1997. The technique described therein employs a remote plasma with self-bias. In this case, the equipment provides a plasma where ions will reach the wafer, however, the ion density at the wafer will be less than that of the source of the plasma. This technique relies upon the self-bias of the wafer, for example, by allowing the wafer to electrically "float", to control ion energy.
The work presented in these publications is also limited to very specific applications. The self-bias value depends upon the construction of a particular plasma reactor (processing chamber) and the chosen process parameters that might affect the nitridization reproducibility, including the nature of the wafer surface. The required configurations cannot be determined ab initio using this remote plasma with self-bias system.
Composite dielectric layers have also been proposed, for example, by U.S. Pat. Nos. 5,258,333 and 5,464,783. The '333 patent discloses a process of thermal nitridization of a silicon substrate in pure ammonia, followed by CVD deposition and optional thermal nitridization in N.sub.2 of a high temperature oxide layer. The '783 patent involves the formation of an oxynitride layer on a silicon substrate, such as by a thermal anneal in an oxygen and nitrogen-containing atmosphere or by a CVD system using oxygen and nitrogen with silane, dichlorosilane, disilane, or SiCl.sub.4 followed by a thermal oxidation step to form an oxide layer at the substrate-oxynitride interface. However, the processes described in these patents rely upon nitridization techniques which do not provide a high degree of control over the incorporation of nitrogen in an oxynitride layer, and are unable to achieve high levels of nitrogen incorporation (i.e., greater than about 10%) in the final oxynitride layer of the composite.
Accordingly, improved nitridization methods for producing hardened thin oxide layers in semiconductor devices without adverse consequences for semiconductor cells would be desirable, particularly as semiconductor device sizes scale below 0.25 .mu.m.